The present invention generally relates to electronic circuit design tools, and more particularly to assisting a designer in the process of developing physical implementation characteristics of a circuit in conjunction with developing the logical characteristics of the circuit.
Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
As FPGA designs increase in complexity, they reach a point at which the designer cannot deal with the entire design at the gate level. Where once a typical FPGA design comprised perhaps 5,000 gates, FPGA designs with 50,000 gates are now common, and FPGAs supporting over 300,000 gates are available. To deal with this complexity, circuits are typically partitioned into smaller circuits that are more easily handled. Often, these smaller circuits are divided into yet smaller circuits, imposing on the design a multi-level hierarchy of logical blocks.
Libraries of pre-developed blocks of logic have been developed that can be included in an FPGA design. Such library modules include, for example, adders, multipliers, filters, and other arithmetic and DSP functions from which system designs can be readily constructed. The engineering community sometimes refers to these previously created designs as xe2x80x9cdesign modulesxe2x80x9d, xe2x80x9ccoresxe2x80x9d or xe2x80x9cIPxe2x80x9d (intellectual property). The use of pre-developed logic cores permits faster design cycles by eliminating the redesign of circuits. Thus, using cores from a library may reduce design costs.
Developing logic cores that are suitable for various applications is challenging because many high-performance FPGA circuits require customized layouts to achieve required performance levels. While various methods are available that allow a logic core designer to exercise various levels of control over the layout of a core, the effort required of the core designer is considerable when high-level hardware description languages are used.
Hardware description languages (HDL) such as VHDL are often used in creating logic cores. An advantage of using HDL is that the circuit can be defined using high-level abstract statements, thereby allowing the specification of complex functions. After the function of a core has been specified in HDL and compiled, the designer verifies correct operation of the core using a simulator such as ModelSim in conjunction with a test bench. This simulation is called a functional simulation and is used to uncover the logical errors in a design. After discovering a logic error, the designer changes the HDL code to fix the problem(s), and again performs a functional simulation. The process is repeated until the designer is satisfied with the logic. During the phase of development that includes design capture and functional simulation, the physical characteristics of the design are generally not examined. Not until the next phase of development, which is the implementation phase, is it known whether the design will satisfy various physical parameters such as chip area and timing. During the implementation phase, the design is synthesized into a lower-level, technology-specific representation, such as an FPGA or ASIC netlist. For FPGAs, the implementation phase also includes mapping the netlist to particular configurable resources of the device. The mapped design is then simulated (physical simulation) to verify that the mapped design retains all the logical characteristics of the original HDL specification, and that the physical aspects of the mapped design have not introduced any new, undesirable, logical characteristics.
If errors are discovered in physical simulation or if the timing data does not satisfy the required timing constraints, the design must be modified. One difficulty in changing the design, at this phase is that the HDL design has been translated to a netlist, and information from the physical simulation is in relationship to the netlist. Thus, in order to resolve a problem the designer must manually trace the netlist back to the original HDL. As further steps in the implementation phase are performed, for example, optimization and place-and-route, the resulting representation of the design becomes further removed from the original HDL. Significant effort may therefore be required to resolve problems identified later in the implementation phase.
Physical problems associated with a design, for example, timing and placement, can often be traced back to the high-level specification of the circuit design. However, timing and placement problems are generally discovered during the implementation phase of the design process where correlating a physical problem with a particular portion of a high-level specification can be a laborious procedure. The numerous transformations of the high-level design into other lower-level representations makes very difficult tracing back low-level design features to high-level design statements.
A method that addresses the aforementioned problems, as well as other related problems, is therefore desirable.
In various embodiments, the invention provides a circuit designer with the means to visualize and control certain aspects of the design""s physical implementation in the context of the original high-level design definition.
In various embodiments, an application programming interface (API) is programmed in a hardware definition language (HDL). The API provides placement directives that can be called from the HDL code that defines functional characteristics of the circuit. The API can also be used in a testbench in order to analyze both the functional and physical placement characteristics of the design. Since the API is programmed in HDL, the placement generated during the implementation phase is the same as the placement analyzed during functional simulation.
The invention supports manipulation of objects in a design""s logical hierarchy to produce a separate physical hierarchy of objects. Placement directives can then be applied to the objects in the physical hierarchy for specifying a physical layout. While adherence to a design""s logical hierarchy is seldom suitable for physically placing objects of the design, individual objects at different levels in the logical hierarchy may be convenient for identifying objects and grouping the objects into a separate physical hierarchy. Thus, the invention provides a convenient method for using objects of the logical hierarchy to create a separate physical hierarchy, and directing placement relationships between the objects in the physical hierarchy.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.